ATmega48PA/88PA/168PA/328P
Table 17-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-
rect PWM mode.
Table 17-4. Compare Output Mode, Phase Correct PWM Mode(1)
COM2A1
COM2A0
Description
0
0
Normal port operation, OC2A disconnected.
WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
0
1
1
1
0
1
Clear OC2A on Compare Match when up-counting. Set OC2A on
Compare Match when down-counting.
Set OC2A on Compare Match when up-counting. Clear OC2A on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on
page 152 for more details.
• Bits 5:4 – COM2B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0
bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin
must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting. Table 17-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
Table 17-5. Compare Output Mode, non-PWM Mode
COM2B1
COM2B0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC2B disconnected.
Toggle OC2B on Compare Match
Clear OC2B on Compare Match
Set OC2B on Compare Match
Table 17-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM
mode.
Table 17-6. Compare Output Mode, Fast PWM Mode(1)
COM2B1
COM2B0
Description
0
0
0
1
Normal port operation, OC2B disconnected.
Reserved
Clear OC2B on Compare Match, set OC2B at BOTTOM,
(non-inverting mode).
1
1
0
1
Set OC2B on Compare Match, clear OC2B at BOTTOM,
(inverting mode).
159
8161D–AVR–10/09
ATMEL [ ATMEL ]
