ATmega16/32/64/M1/C1
• PCINT0/MISO/PSCOUT2A – Bit 0
MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
master, this pin is configured as an input regardless of the setting of DDB0. When the SPI is
enabled as a slave, the data direction of this pin is controlled by DDB0. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTB0 and PUD bits.
PSCOUT2A, Output 2A of PSC.
PCINT0, Pin Change Interrupt 0.
Table 9-4 and Table 9-5 relates the alternate functions of Port B to the overriding signals shown
in Figure 9-5 on page 67.
Table 9-4.
Overriding Signals for Alternate Functions in PB7..PB4
PB6/ADC7/
PSCOUT1B/
PCINT6
PB7/ADC4/
PB5/ADC6/
PB4/AMP0+/
PCINT4
PSCOUT0B/SCK/
PCINT7
INT2/ACMPN1/
AMP2-/PCINT5
Signal Name
PUOE
SPE • MSTR • SPIPS
PB7 • PUD • SPIPS
0
0
0
0
0
0
PUOV
SPE • MSTR • SPIPS
+ PSCen01
DDOE
PSCen11
0
0
DDOV
PVOE
PSCen01
1
0
0
0
0
SPE • MSTR • SPIPS PSCen11
PSCout01 • SPIPS +
PSCout01 • PSCen01 •
SPIPS
PVOV
PSCOUT11
0
0
+ PSCout01 •
PSCen01 • SPIPS
DIEOE
DIEOV
DI
ADC4D
0
ADC7D
0
ADC6D + In2en
In2en
AMP0ND
0
SCKin • SPIPS • ireset ICP1B
ADC4 ADC7
INT2
AIO
ADC6
AMP0+
Table 9-5.
Overriding Signals for Alternate Functions in PB3..PB0
PB1/MOSI/
PB0/MISO/
PSCOUT2A/
PCINT0
PB3/AMP0-/
PCINT3
PB2/ADC5/INT1/
ACMPN0/PCINT2
PSCOUT2B/
PCINT1
Signal Name
PUOE
0
0
–
–
–
–
–
–
0
0
–
–
–
–
–
–
0
0
PUOV
0
0
DDOE
0
0
DDOV
0
0
PVOE
0
0
PVOV
0
0
DIEOE
DIEOV
AMP0ND
0
ADC5D + In1en
In1en
MOSI_IN • SPIPS • MISO_IN • SPIPS •
DI
INT1
ireset
ireset
AIO
AMP0-
ADC5
–
–
71
7647F–AVR–04/09
ATMEL [ ATMEL ]
