Figure 7-5. Brown-out Reset During Operation
VBOT+
VCC
VBOT-
RESET
t
TOUT
TIME-OUT
INTERNAL
RESET
7.2.4
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to
page 52 for details on operation of the Watchdog Timer.
Figure 7-6. Watchdog Reset During Operation
CC
CK
7.2.5
MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
WDRF
R/W
BORF
R/W
EXTRF
PORF
R/W
MCUSR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R/W
See Bit Description
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
50
ATmega16/32/64/M1/C1
7647F–AVR–04/09
ATMEL [ ATMEL ]
