Figure 7-2. MCU Start-up, RESET Tied to VCC
V
CCRR
VCC
VPORMAX
VPORMIN
RESET
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 7-3. MCU Start-up, RESET Extended Externally
VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
7.2.2
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 7-1) will generate a reset, even if the clock is not running.
Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the
Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after
the Time-out period – tTOUT – has expired.
Figure 7-4. External Reset During Operation
CC
48
ATmega16/32/64/M1/C1
7647F–AVR–04/09
ATMEL [ ATMEL ]
