16.9 CAN Register Description
Figure 16-15. Registers Organization
AVR Registers
Registers in Pages
General Control
General Status
General Interrupt
Bit Timing 1
Bit Timing 2
Bit Timing 3
Enable MOb 2
Enable MOb 1
Enable Interrupt
Enable Interrupt MOb 2
Enable Interrupt MOb 1
Status Interrupt MOb 2
Status Interrupt MOb 1
CAN Timer Control
CAN Timer Low
CAN Timer High
CAN TTC Low
CAN TTC High
TEC Counter
REC Counter
Hightest Priority MOb
Page MOb
MOb(i) - MOb Status
MOb Number
Data Index
MOb(i) - MOb Ctrl & DLC
MOb(i) - ID Tag 4
MOb(i) - ID Tag 3
MOb(i) - ID Tag 2
MOb(i) - ID Tag 1
Page MOb
MOb Status
MOb0 - MOb Status
MOb Control & DLC
MOb0 - MOb Ctrl & DLC
MOb(i) - ID Mask 4
MOb(i) - ID Mask 3
MOb(i) - ID Mask 2
MOb(i) - ID Mask 1
ID Tag 4
ID Tag 3
ID Tag 2
ID Tag 1
MOb0 - ID Tag 4
MOb0 - ID Tag 3
MOb0 - ID Tag 2
MOb0 - ID Tag 1
MOb(i)
MOb(i)
-
-
Time Stamp Low
Time Stamp High
ID Mask 4
ID Mask 3
ID Mask 2
ID Mask 1
MOb0 - ID Mask 4
MOb0 - ID Mask 3
MOb0 - ID Mask 2
MOb0 - ID Mask 1
MOb(i)
-
Mess. Data - byte 0
Time Stamp Low
Time Stamp High
MOb0 - Time Stamp Low
MOb0 - Time Stamp High
Message Data
MOb0 - Mess. Data - byte 0
8 bytes
186
ATmega16/32/64/M1/C1
7647F–AVR–04/09
ATMEL [ ATMEL ]
