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ATMEGA16M1_1 参数 Datasheet PDF下载

ATMEGA16M1_1图片预览
型号: ATMEGA16M1_1
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有16K / 32K / 64K字节的系统内可编程闪存 [8-bit Microcontroller with 16K/32K/64K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 365 页 / 6381 K
品牌: ATMEL [ ATMEL ]
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16.2.3.7  
16.2.3.8  
Information Processing Time  
It is the time required for the logic to determine the bit level of a sampled bit.  
The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN.  
Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time,  
PS2 minimum shall not be less than the IPT.  
Bit Lengthening  
As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2  
may be shortened to compensate for oscillator tolerances. If, for example, the transmitter oscilla-  
tor is slower than the receiver oscillator, the next falling edge used for resynchronization may be  
delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of  
the bit time.  
16.2.3.9  
Bit Shortening  
If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling  
edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in  
order to adjust the sample point for bit N+1 and the end of the bit time  
16.2.3.10  
Synchronization Jump Width  
The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resyn-  
chronization Jump Width.  
This segment may not be longer than Phase Segment 2.  
16.2.3.11  
Programming the Sample Point  
Programming of the sample point allows "tuning" of the characteristics to suit the bus.  
Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchronization Jump  
Width can be programmed to its maximum. This maximum capacity to shorten or lengthen the  
bit time decreases the sensitivity to node oscillator tolerances, so that lower cost oscillators such  
as ceramic resonators may be used.  
Late sampling allows more Time Quanta in the Propagation Time Segment which allows a  
poorer bus topology and maximum bus length.  
16.2.3.12  
Synchronization  
Hard synchronization occurs on the recessive-to-dominant transition of the start bit. The bit time  
is restarted from that edge.  
Re-synchronization occurs when a recessive-to-dominant edge doesn't occur within the Syn-  
chronization Segment in a message.  
16.2.4  
Arbitration  
The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple  
Access with Arbitration on Message Priority”.  
During transmission, arbitration on the CAN bus can be lost to a competing device with a higher  
priority CAN Identifier. This arbitration concept avoids collisions of messages whose transmis-  
sion was started by more than one node simultaneously and makes sure the most important  
message is sent first without time loss.  
172  
ATmega16/32/64/M1/C1  
7647F–AVR–04/09  
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