ATmega16/32/64/M1/C1
Table 13-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM(1)
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
0
Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 8, 9 10 or 11: Toggle OCnA on Compare
Match, OCnB disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
0
1
Clear OCnA/OCnB on Compare Match when
up-counting. Set OCnA/OCnB on Compare Match
when downcounting.
1
1
0
1
Set OCnA/OCnB on Compare Match when
up-counting. Clear OCnA/OCnB on Compare Match
when downcounting.
Note:
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See
“Phase Correct PWM Mode” on page 123. for more details.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 13-4. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes. (See “16-bit Timer/Counter1 with PWM” on page
107.).
Table 13-4. Waveform Generation Mode Bit Description(1)
WGMn2 WGMn1 WGMn0
(CTCn) (PWMn1) (PWMn0) Timer/Counter Mode of Operation TOP
Update of
OCRnx at
TOVn Flag
Set on
Mode WGMn3
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Normal
0xFFFF
0x00FF
0x01FF
0x03FF
OCRnA
0x00FF
0x01FF
0x03FF
Immediate
TOP
MAX
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
BOTTOM
BOTTOM
BOTTOM
MAX
2
TOP
3
TOP
4
Immediate
TOP
5
Fast PWM, 8-bit
TOP
6
Fast PWM, 9-bit
TOP
TOP
7
Fast PWM, 10-bit
TOP
TOP
8
PWM, Phase and Frequency Correct ICRn
PWM, Phase and Frequency Correct OCRnA
BOTTOM
BOTTOM
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
MAX
9
10
11
12
13
14
15
Note:
PWM, Phase Correct
PWM, Phase Correct
CTC
ICRn
OCRnA
ICRn
–
TOP
Immediate
–
(Reserved)
–
Fast PWM
ICRn
OCRnA
TOP
TOP
Fast PWM
TOP
TOP
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
131
7647F–AVR–04/09
ATMEL [ ATMEL ]
