ATmega16(L)
Data Memory Access
Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in
Figure 10.
On-chip Data SRAM Access Cycles
T1
T2
T3
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Address Valid
Memory Access Instruction
Next Instruction
EEPROM Data
Memory
The ATmega16 contains 512 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
For a detailed description of SPI, JTAG, and Parallel data downloading to the EEPROM, see
and
respectively.
EEPROM Read/Write
Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used. See
for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
Read
Write
18
2466S–AVR–05/09
ATMEL [ ATMEL CORPORATION ]
