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ATMEGA8A-AUR 参数 Datasheet PDF下载

ATMEGA8A-AUR图片预览
型号: ATMEGA8A-AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ABA, TQFP-32]
分类和应用: 闪存
文件页数/大小: 308 页 / 4674 K
品牌: ATMEL [ ATMEL ]
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ATmega8(L)  
Figure 102. Memory Sections(1)  
Program Memory  
BOOTSZ = '10'  
Program Memory  
BOOTSZ = '11'  
$0000  
$0000  
Application Flash Section  
Application Flash Section  
End RWW  
End RWW  
Start NRWW  
Start NRWW  
Application Flash Section  
Boot Loader Flash Section  
Application Flash Section  
Boot Loader Flash Section  
End Application  
End Application  
Start Boot Loader  
Flashend  
Start Boot Loader  
Flashend  
$0000  
Program Memory  
BOOTSZ = '01'  
Program Memory  
BOOTSZ = '00'  
$0000  
Application Flash Section  
Application flash Section  
End RWW, End Application  
End RWW  
Start NRWW, Start Boot Loader  
Start NRWW  
Application Flash Section  
Boot Loader Flash Section  
End Application  
Boot Loader Flash Section  
Start Boot Loader  
Flashend  
Flashend  
Note:  
1. The parameters in the figure are given in Table 82 on page 220.  
Boot Loader Lock If no Boot Loader capability is needed, the entire Flash is available for application code. The  
Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives  
the user a unique flexibility to select different levels of protection.  
Bits  
The user can select:  
To protect the entire Flash from a software update by the MCU.  
To protect only the Boot Loader Flash section from a software update by the MCU.  
To protect only the Application Flash section from a software update by the MCU.  
Allow software update in the entire Flash.  
See Table 78 and Table 79 for further details. The Boot Lock Bits can be set in software and in  
Serial or Parallel Programming mode, but they can be cleared by a chip erase command only.  
The general Write Lock (Lock bit mode 2) does not control the programming of the Flash mem-  
ory by SPM instruction. Similarly, the general Read/Write Lock (Lock bit mode 3) does not  
control reading nor writing by LPM/SPM, if it is attempted.  
211  
2486T–AVR–05/08  
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