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ATMEGA48V-10MMHR 参数 Datasheet PDF下载

ATMEGA48V-10MMHR图片预览
型号: ATMEGA48V-10MMHR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQCC28, 4 X 4 MM, 1 MM HEIGHT, 0.45 MM PITCH, GREEN, PLASTIC, VQFN-28]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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ATmega48/88/168  
7.6  
Register Description  
7.6.1  
EEARH and EEARL – The EEPROM Address Register  
Bit  
15  
14  
13  
12  
11  
10  
9
8
EEAR8  
EEAR0  
0
0x22 (0x42)  
0x21 (0x41)  
EEARH  
EEARL  
EEAR7  
EEAR6  
EEAR5  
EEAR4  
EEAR3  
EEAR2  
EEAR1  
7
R
6
R
5
R
4
R
3
R
2
R
1
R
Read/Write  
Initial Value  
R/W  
R/W  
X
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
X
X
X
X
X
X
X
X
• Bits 15..9 – Res: Reserved Bits  
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.  
• Bits 8..0 – EEAR8..0: EEPROM Address  
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the  
256/512/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0  
and 255/511/511. The initial value of EEAR is undefined. A proper value must be written before  
the EEPROM may be accessed.  
EEAR8 is an unused bit in ATmega48 and must always be written to zero.  
7.6.2  
EEDR – The EEPROM Data Register  
Bit  
0x20 (0x40)  
7
6
5
4
3
2
1
0
MSB  
LSB  
R/W  
0
EEDR  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
• Bits 7..0 – EEDR7.0: EEPROM Data  
For the EEPROM write operation, the EEDR Register contains the data to be written to the  
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the  
EEDR contains the data read out from the EEPROM at the address given by EEAR.  
7.6.3  
EECR – The EEPROM Control Register  
Bit  
0x1F (0x3F)  
7
6
5
EEPM1  
R/W  
X
4
EEPM0  
R/W  
X
3
EERIE  
R/W  
0
2
EEMPE  
R/W  
0
1
EEPE  
R/W  
X
0
EERE  
R/W  
0
EECR  
Read/Write  
Initial Value  
R
0
R
0
• Bits 7..6 – Res: Reserved Bits  
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.  
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits  
The EEPROM Programming mode bit setting defines which programming action that will be trig-  
gered when writing EEPE. It is possible to program data in one atomic operation (erase the old  
value and program the new value) or to split the Erase and Write operations in two different  
operations. The Programming times for the different modes are shown in Table 7-1. While EEPE  
23  
2545M–AVR–09/07  
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