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ATMEGA48V-10MMHR 参数 Datasheet PDF下载

ATMEGA48V-10MMHR图片预览
型号: ATMEGA48V-10MMHR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQCC28, 4 X 4 MM, 1 MM HEIGHT, 0.45 MM PITCH, GREEN, PLASTIC, VQFN-28]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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ATmega48/88/168  
Figure 7-4. On-chip Data SRAM Access Cycles  
T1  
T2  
T3  
clkCPU  
Address valid  
Compute Address  
Address  
Data  
WR  
Data  
RD  
Memory Access Instruction  
Next Instruction  
7.4  
EEPROM Data Memory  
The ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory. It is organized  
as a separate data space, in which single bytes can be read and written. The EEPROM has an  
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the  
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM  
Data Register, and the EEPROM Control Register.  
“Memory Programming” on page 286 contains a detailed description on EEPROM Programming  
in SPI or Parallel Programming mode.  
7.4.1  
EEPROM Read/Write Access  
The EEPROM Access Registers are accessible in the I/O space.  
The write access time for the EEPROM is given in Table 7-2. A self-timing function, however,  
lets the user software detect when the next byte can be written. If the user code contains instruc-  
tions that write the EEPROM, some precautions must be taken. In heavily filtered power  
supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some  
period of time to run at a voltage lower than specified as minimum for the clock frequency used.  
See “Preventing EEPROM Corruption” on page 21 for details on how to avoid problems in these  
situations.  
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.  
Refer to the description of the EEPROM Control Register for details on this.  
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is  
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next  
instruction is executed.  
7.4.2  
Preventing EEPROM Corruption  
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is  
too low for the CPU and the EEPROM to operate properly. These issues are the same as for  
board level systems using EEPROM, and the same design solutions should be applied.  
21  
2545M–AVR–09/07  
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