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ATMEGA48V-10MMHR 参数 Datasheet PDF下载

ATMEGA48V-10MMHR图片预览
型号: ATMEGA48V-10MMHR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 10MHz, CMOS, PQCC28, 4 X 4 MM, 1 MM HEIGHT, 0.45 MM PITCH, GREEN, PLASTIC, VQFN-28]
分类和应用: 闪存微控制器
文件页数/大小: 376 页 / 4764 K
品牌: ATMEL [ ATMEL ]
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7.3  
SRAM Data Memory  
Figure 7-3 shows how the ATmega48/88/168 SRAM Memory is organized.  
The ATmega48/88/168 is a complex microcontroller with more peripheral units than can be sup-  
ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the  
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-  
tions can be used.  
The lower 768/1280/1280 data memory locations address both the Register File, the I/O mem-  
ory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the  
Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O  
memory, and the next 512/1024/1024 locations address the internal data SRAM.  
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-  
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register  
File, registers R26 to R31 feature the indirect addressing pointer registers.  
The direct addressing reaches the entire data space.  
The Indirect with Displacement mode reaches 63 address locations from the base address given  
by the Y- or Z-register.  
When using register indirect addressing modes with automatic pre-decrement and post-incre-  
ment, the address registers X, Y, and Z are decremented or incremented.  
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and  
the 512/1024/1024 bytes of internal data SRAM in the ATmega48/88/168 are all accessible  
through all these addressing modes. The Register File is described in “General Purpose Regis-  
ter File” on page 13.  
Figure 7-3. Data Memory Map  
Data Memory  
0x0000 - 0x001F  
0x0020 - 0x005F  
0x0060 - 0x00FF  
32 Registers  
64 I/O Registers  
160 Ext I/O Reg.  
0x0100  
Internal SRAM  
(512/1024/1024 x 8)  
0x02FF/0x04FF/0x04FF  
7.3.1  
Data Memory Access Times  
This section describes the general access timing concepts for internal memory access. The  
internal data SRAM access is performed in two clkCPU cycles as described in Figure 7-4.  
20  
ATmega48/88/168  
2545M–AVR–09/07  
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