ATmega48/88/168
Table 14-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Table 14-4. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
Description
0
0
Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
0
1
1
1
0
1
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 124 for more details.
• Bits 5:4 – COM0B1:0: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. Table 14-5 shows the COM0B1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-5. Compare Output Mode, non-PWM Mode
COM0B1
COM0B0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0B disconnected.
Toggle OC0B on Compare Match
Clear OC0B on Compare Match
Set OC0B on Compare Match
Table 14-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
mode.
Table 14-6. Compare Output Mode, Fast PWM Mode(1)
COM0B1
COM0B0
Description
0
0
0
1
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match, set OC0B at BOTTOM,
(non-inverting mode)
1
1
0
1
Set OC0B on Compare Match, clear OC0B at BOTTOM,
(inverting mode)
103
2545M–AVR–09/07
ATMEL [ ATMEL ]
