ATmega8(L)
Data Memory Access
Times
This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clkCPU cycles as described in Figure
9.
Figure 9. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address Valid
Compute Address
Address
Data
WR
Data
RD
Memory Vccess Instruction
Next Instruction
EEPROM Data Memory
The ATmega8 contains 512 bytes of data EEPROM memory. It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM
and the CPU is described bellow, specifying the EEPROM Address Registers, the
EEPROM Data Register, and the EEPROM Control Register.
“Memory Programming” on page 219 contains a detailed description on EEPROM Pro-
gramming in SPI- or Parallel Programming mode.
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1 on page 19. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that write the EEPROM, some precautions must be
taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See “Preventing EEPROM Corrup-
tion” on page 21. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
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2486M–AVR–12/03
ATMEL [ ATMEL ]
