ATmega8(L)
Table 39. Waveform Generation Mode Bit Description (Continued)
WGM12
(CTC1)
WGM11
WGM10
Timer/Counter Mode of
Update of
OCR1x
TOV1 Flag
Set on
Mode WGM13
(PWM11) (PWM10) Operation(1)
TOP
7
8
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Fast PWM, 10-bit
0x03FF
BOTTOM
BOTTOM
TOP
PWM, Phase and Frequency Correct ICR1
BOTTOM
BOTTOM
BOTTOM
BOTTOM
MAX
9
PWM, Phase and Frequency Correct OCR1A BOTTOM
10
PWM, Phase Correct
PWM, Phase Correct
CTC
ICR1
TOP
11
OCR1A TOP
12
ICR1
–
Immediate
13
(Reserved)
–
–
14
Fast PWM
ICR1
BOTTOM
TOP
15
Fast PWM
OCR1A BOTTOM
TOP
Note:
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer
Timer/Counter 1
Control Register B –
TCCR1B
Bit
7
ICNC1
R/W
0
6
ICES1
R/W
0
5
–
4
WGM13
R/W
0
3
WGM12
R/W
0
2
CS12
R/W
0
1
CS11
R/W
0
0
CS10
R/W
0
TCCR1B
Read/Write
Initial Value
R
0
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure
41 on page 94 and Figure 42 on page 94.
98
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
