欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA8L-8MUR 参数 Datasheet PDF下载

ATMEGA8L-8MUR图片预览
型号: ATMEGA8L-8MUR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位爱特梅尔带有8K字节的系统内可编程闪存 [8-bit Atmel with 8KBytes In-System PRogrammable Flash]
分类和应用: 闪存微控制器和处理器外围集成电路异步传输模式PCATM时钟
文件页数/大小: 331 页 / 6705 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA8L-8MUR的Datasheet PDF文件第78页浏览型号ATMEGA8L-8MUR的Datasheet PDF文件第79页浏览型号ATMEGA8L-8MUR的Datasheet PDF文件第80页浏览型号ATMEGA8L-8MUR的Datasheet PDF文件第81页浏览型号ATMEGA8L-8MUR的Datasheet PDF文件第83页浏览型号ATMEGA8L-8MUR的Datasheet PDF文件第84页浏览型号ATMEGA8L-8MUR的Datasheet PDF文件第85页浏览型号ATMEGA8L-8MUR的Datasheet PDF文件第86页  
ATmega8(L)  
The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the  
signal applied. Alternatively the time-stamps can be used for creating a log of the events.  
The Input Capture unit is illustrated by the block diagram shown in Figure 34. The elements of  
the block diagram that are not directly a part of the Input Capture unit are gray shaded. The  
small “n” in register and bit names indicates the Timer/Counter number.  
Figure 34. Input Capture Unit Block Diagram  
DATA BUS (8-bit)  
TEMP (8-bit)  
ICRnH (8-bit)  
ICRnL (8-bit)  
TCNTnH (8-bit)  
TCNTnL (8-bit)  
ICRn (16-bit Register)  
TCNTn (16-bit Counter)  
WRITE  
ACO*  
ACIC*  
ICNC  
ICES  
Analog  
Comparator  
Noise  
Canceler  
Edge  
Detector  
ICFn (Int. Req.)  
ICPn  
When a change of the logic level (an event) occurs on the Input Capture Pin (ICP1), alternatively  
on the Analog Comparator Output (ACO), and this change confirms to the setting of the edge  
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter  
(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at  
the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (TICIE1 =  
1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically  
cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software  
by writing a logical one to its I/O bit location.  
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low  
byte (ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied  
into the High byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will  
access the TEMP Register.  
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes  
the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-  
tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1  
Register. When writing the ICR1 Register the High byte must be written to the ICR1H I/O loca-  
tion before the Low byte is written to ICR1L.  
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”  
on page 77.  
Input Capture Pin  
Source  
The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter  
1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture  
82  
2486AA–AVR–02/2013  
 复制成功!