ATmega8(L)
Figure 33. Counter Unit Block Diagram
DATA BUS (8-bit)
TOVn
(Int. Req.)
TEMP (8-bit)
Clock Select
count
Edge
Detector
Tn
TCNTnH (8-bit) TCNTnL (8-bit)
TCNTn (16-bit Counter)
clear
clkTn
Control Logic
direction
( From Prescaler )
TOP
BOTTOM
Signal description (internal signals):
count
Increment or decrement TCNT1 by 1
direction Select between increment and decrement
clear
Clear TCNT1 (set all bits to zero)
Timer/Counter clock
clkT
1
TOP
Signalize that TCNT1 has reached maximum value
BOTTOM Signalize that TCNT1 has reached minimum value (zero)
The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) con-
taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the High byte temporary register
(TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read,
and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows
the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data
bus. It is important to notice that there are special cases of writing to the TCNT1 Register when
the counter is counting that will give unpredictable results. The special cases are described in
the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk ). The clk 1 can be generated from an external or internal clock source,
1
T
T
selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clkT is present or not. A CPU write overrides (has priority over) all counter clear or
1
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare Outputs OC1x. For more details about advanced count-
ing sequences and waveform generation, see “Modes of Operation” on page 87.
The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operation selected by
the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-
tiple events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit.
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2486AA–AVR–02/2013
ATMEL [ ATMEL ]
