ATmega8(L)
• Bit 0 – UCPOL: Clock Polarity
This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is
used. The UCPOL bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCK).
Table 59. UCPOL Bit Settings
Transmitted Data Changed
UCPOL (Output of TxD Pin)
Received Data Sampled
(Input on RxD Pin)
0
1
Rising XCK Edge
Falling XCK Edge
Falling XCK Edge
Rising XCK Edge
USART Baud Rate
Registers – UBRRL
and UBRRHs
Bit
15
14
13
12
11
10
9
8
URSEL
–
–
–
UBRR[11:8]
UBRRH
UBRRL
UBRR[7:0]
7
R/W
R/W
0
6
R
5
R
4
R
3
R/W
R/W
0
2
R/W
R/W
0
1
R/W
R/W
0
0
R/W
R/W
0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
0
0
0
0
0
0
0
0
The UBRRH Register shares the same I/O location as the UCSRC Register. See the “Accessing
UBRRH/UCSRC Registers” on page 146 section which describes how to access this register.
• Bit 15 – URSEL: Register Select
This bit selects between accessing the UBRRH or the UCSRC Register. It is read as zero when
reading UBRRH. The URSEL must be zero when writing the UBRRH.
• Bit 14:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bits, and the UBRRL contains the eight least significant bits of the USART baud
rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
152
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
