ATmega8(L)
• Bit 3 – TXEN: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero)
will not become effective until ongoing and pending transmissions are completed (that is, when
the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted).
When disabled, the Transmitter will no longer override the TxD port.
• Bit 2 – UCSZ2: Character Size
The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char-
acter Size) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8: Receive Data Bit 8
RXB8 is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDR.
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDR.
USART Control and
Status Register C –
UCSRC
Bit
7
URSEL
R/W
1
6
UMSEL
R/W
0
5
UPM1
R/W
0
4
UPM0
R/W
0
3
USBS
R/W
0
2
UCSZ1
R/W
1
1
UCSZ0
R/W
1
0
UCPOL
R/W
0
UCSRC
Read/Write
Initial Value
The UCSRC Register shares the same I/O location as the UBRRH Register. See the “Accessing
UBRRH/UCSRC Registers” on page 146 section which describes how to access this register.
• Bit 7 – URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when
reading UCSRC. The URSEL must be one when writing the UCSRC.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
Table 55. UMSEL Bit Settings
UMSEL
Mode
0
1
Asynchronous Operation
Synchronous Operation
150
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
