ATmega8(L)
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
46 shows a block diagram of the counter and its surrounding environment.
Figure 46. Counter Unit Block Diagram
TOVn
(Int. Req.)
DATA BUS
TOSC1
count
T/C
Oscillator
clk Tn
clear
TCNTn
Control Logic
Prescaler
direction
TOSC2
BOTTOM
TOP
clk
I/O
Signal description (internal signals):
count Increment or decrement TCNT2 by 1
direction Selects between increment and decrement
clear
clkT2
TOP
Clear TCNT2 (set all bits to zero)
Timer/Counter clock
Signalizes that TCNT2 has reached maximum value
BOTTOM Signalizes that TCNT2 has reached minimum value (zero)
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source,
selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the Output Compare Output
OC2. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page 108.
The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.
104
2486AA–AVR–02/2013
ATMEL [ ATMEL ]
