Table 28. Reset and Interrupt Vectors Placement in ATmega88(1)
BOOTRST
IVSEL
Reset Address
0x000
Interrupt Vectors Start Address
0x001
1
1
0
0
0
1
0
1
0x000
Boot Reset Address + 0x001
0x001
Boot Reset Address
Boot Reset Address
Boot Reset Address + 0x001
Note:
1. The Boot Reset Address is shown in Table 109 on page 268. For the BOOTRST
Fuse “1” means unprogrammed while “0” means programmed.
The most typical and general program setup for the Reset and Interrupt Vector
Addresses in ATmega88 is:
Address Labels Code
Comments
0x000
0x001
0x002
0x003
0x004
0x005
0x006
0x007
0X008
0x009
0x00A
0x00B
0x00C
0x00D
0x00E
0x00F
0x010
0x011
0x012
0x013
0x014
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
RESET
; Reset Handler
EXT_INT0
EXT_INT1
PCINT0
; IRQ0 Handler
; IRQ1 Handler
; PCINT0 Handler
PCINT1
; PCINT1 Handler
PCINT2
; PCINT2 Handler
WDT
; Watchdog Timer Handler
; Timer2 Compare A Handler
; Timer2 Compare B Handler
; Timer2 Overflow Handler
; Timer1 Capture Handler
; Timer1 Compare A Handler
; Timer1 Compare B Handler
; Timer1 Overflow Handler
; Timer0 Compare A Handler
; Timer0 Compare B Handler
; Timer0 Overflow Handler
; SPI Transfer Complete Handler
; USART, RX Complete Handler
; USART, UDR Empty Handler
; USART, TX Complete Handler
; ADC Conversion Complete
TIM2_COMPA
TIM2_COMPB
TIM2_OVF
TIM1_CAPT
TIM1_COMPA
TIM1_COMPB
TIM1_OVF
TIM0_COMPA
TIM0_COMPB
TIM0_OVF
SPI_STC
USART_RXC
USART_UDRE
USART_TXC
ADC
0x015
Handler
0x016
0x017
rjmp
rjmp
rjmp
EE_RDY
ANA_COMP
TWI
; EEPROM Ready Handler
; Analog Comparator Handler
; 2-wire Serial Interface
0x018
Handler
0x019
rjmp
SPM_RDY
; Store Program Memory Ready
Handler
;
0x01ARESET:
ldi
out
r16, high(RAMEND); Main program start
SPH,r16 ; Set Stack Pointer to top of
0x01B
RAM
0x01C
ldi
r16, low(RAMEND)
54
ATmega48/88/168
2545D–AVR–07/04
ATMEL [ ATMEL ]
