USART Register
Description
USART I/O Data Register n–
UDRn
Bit
7
6
5
4
3
2
1
0
RXB[7:0]
TXB[7:0]
UDRn (Read)
UDRn (Write)
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers
share the same I/O address referred to as USART Data Register or UDRn. The Trans-
mit Data Buffer Register (TXB) will be the destination for data written to the UDRn
Register location. Reading the UDRn Register location will return the contents of the
Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter
and set to zero by the Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register
is set. Data written to UDRn when the UDREn Flag is not set, will be ignored by the
USART Transmitter. When data is written to the transmit buffer, and the Transmitter is
enabled, the Transmitter will load the data into the Transmit Shift Register when the
Shift Register is empty. Then the data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever
the receive buffer is accessed. Due to this behavior of the receive buffer, do not use
Read-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bit
test instructions (SBIC and SBIS), since these also will change the state of the FIFO.
USART Control and Status
Register n A – UCSRnA
Bit
7
RXCn
R
6
TXCn
R/W
0
5
4
FEn
R
3
DORn
R
2
UPEn
R
1
U2Xn
R/W
0
0
MPCMn
R/W
0
UDREn
UCSRnA
Read/Write
Initial Value
R
1
0
0
0
0
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis-
abled, the receive buffer will be flushed and consequently the RXCn bit will become
zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see
description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted
out and there are no new data currently present in the transmit buffer (UDRn). The
TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXCn Flag can generate a
Transmit Complete interrupt (see description of the TXCIEn bit).
180
ATmega48/88/168
2545D–AVR–07/04
ATMEL [ ATMEL ]
