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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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• Bit 2:0 – CS02:0: Clock Select  
The three Clock Select bits select the clock source to be used by the Timer/Counter.  
Table 42. Clock Select Bit Description  
CS02  
CS01  
CS00  
Description  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No clock source (Timer/Counter stopped).  
clkI/O/(No prescaling)  
clkI/O/8 (From prescaler)  
clkI/O/64 (From prescaler)  
clkI/O/256 (From prescaler)  
clkI/O/1024 (From prescaler)  
External clock source on T0 pin. Clock on falling edge.  
External clock source on T0 pin. Clock on rising edge.  
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will  
clock the counter even if the pin is configured as an output. This feature allows software  
control of the counting.  
Timer/Counter Register –  
TCNT0  
Bit  
7
6
5
4
3
2
1
0
TCNT0[7:0]  
TCNT0  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
The Timer/Counter Register gives direct access, both for read and write operations, to  
the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes)  
the compare match on the following timer clock. Modifying the counter (TCNT0) while  
the counter is running, introduces a risk of missing a compare match between TCNT0  
and the OCR0 Register.  
Output Compare Register –  
OCR0  
Bit  
7
6
5
4
3
2
1
0
OCR0[7:0]  
OCR0  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
The Output Compare Register contains an 8-bit value that is continuously compared  
with the counter value (TCNT0). A match can be used to generate an output compare  
interrupt, or to generate a waveform output on the OC0 pin.  
Timer/Counter Interrupt Mask  
Register – TIMSK  
Bit  
7
OCIE2  
R/W  
0
6
TOIE2  
R/W  
0
5
TICIE1  
R/W  
0
4
OCIE1A  
R/W  
0
3
OCIE1B  
R/W  
0
2
TOIE1  
R/W  
0
1
OCIE0  
R/W  
0
0
TOIE0  
R/W  
0
TIMSK  
Read/Write  
Initial Value  
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable  
When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the  
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is  
82  
ATmega32(L)  
2503J–AVR–10/06  
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