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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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ATmega32(L)  
Figure 33. Phase Correct PWM Mode, Timing Diagram  
OCn Interrupt Flag Set  
OCRn Update  
TOVn Interrupt Flag Set  
TCNTn  
(COMn1:0 = 2)  
(COMn1:0 = 3)  
OCn  
OCn  
1
2
3
Period  
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT-  
TOM. The Interrupt Flag can be used to generate an interrupt each time the counter  
reaches the BOTTOM value.  
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on  
the OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM. An  
inverted PWM output can be generated by setting the COM01:0 to 3 (see Table 41 on  
page 81). The actual OC0 value will only be visible on the port pin if the data direction  
for the port pin is set as output. The PWM waveform is generated by clearing (or setting)  
the OC0 Register at the compare match between OCR0 and TCNT0 when the counter  
increments, and setting (or clearing) the OC0 Register at compare match between  
OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output  
when using phase correct PWM can be calculated by the following equation:  
f
clk_I/O  
f
= -----------------  
OCnPCPWM  
N 510  
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).  
The extreme values for the OCR0 Register represent special cases when generating a  
PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to  
BOTTOM, the output will be continuously low and if set equal to MAX the output will be  
continuously high for non-inverted PWM mode. For inverted PWM the output will have  
the opposite logic values.  
At the very start of period 2 in Figure 33 OCn has a transition from high to low even  
though there is no Compare Match. The point of this transition is to guarantee symmetry  
around BOTTOM. There are two cases that give a transition without Compare Match:  
OCR0A changes its value from MAX, like in Figure 33. When the OCR0A value is  
MAX the OCn pin value is the same as the result of a down-counting Compare  
Match. To ensure symmetry around BOTTOM the OCn value at MAX must  
correspond to the result of an up-counting Compare Match.  
77  
2503J–AVR–10/06  
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