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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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Two-wire Serial Interface Characteristics  
Table 119 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega32 Two-wire Serial  
Interface meets or exceeds these requirements under the noted conditions.  
Timing symbols refer to Figure 145.  
Table 119. Two-wire Serial Bus Requirements  
Symbol Parameter  
Condition  
Min  
-0.5  
Max  
0.3 VCC  
VCC + 0.5  
Units  
V
VIL  
Input Low-voltage  
VIH  
Vhys  
Input High-voltage  
0.7 VCC  
V
(1)  
(1)  
(2)  
Hysteresis of Schmitt Trigger Inputs  
Output Low-voltage  
0.05 VCC  
V
VOL  
tr(1)  
3 mA sink current  
10 pF < Cb < 400 pF(3)  
0.1VCC < Vi < 0.9VCC  
0
0.4  
V
(3)(2)  
(3)(2)  
Rise Time for both SDA and SCL  
Output Fall Time from VIHmin to VILmax  
Spikes Suppressed by Input Filter  
Input Current each I/O Pin  
Capacitance for each I/O Pin  
SCL Clock Frequency  
20 + 0.1Cb  
300  
ns  
ns  
ns  
µA  
pF  
kHz  
(1)  
tof  
20 + 0.1Cb  
250  
tSP  
Ii  
Ci(1)  
fSCL  
0
-10  
50(2)  
(1)  
10  
10  
fCK(4) > max(16fSCL, 250kHz)(5)  
0
400  
VCC 0,4V  
----------------------------  
3mA  
fSCL 100 kHz  
1000ns  
Cb  
-------------------  
Ω
Ω
Rp  
Value of Pull-up resistor  
VCC 0,4V  
----------------------------  
3mA  
f
SCL > 100 kHz  
300ns  
---------------  
Cb  
fSCL 100 kHz  
fSCL > 100 kHz  
fSCL 100 kHz(6)  
4.0  
0.6  
4.7  
1.3  
4.0  
0.6  
4.7  
0.6  
0
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
ns  
ns  
µs  
µs  
µs  
µs  
tHD;STA  
Hold Time (repeated) START Condition  
Low Period of the SCL Clock  
tLOW  
f
SCL > 100 kHz(7)  
fSCL 100 kHz  
fSCL > 100 kHz  
fSCL 100 kHz  
fSCL > 100 kHz  
fSCL 100 kHz  
tHIGH  
High period of the SCL clock  
tSU;STA  
tHD;DAT  
tSU;DAT  
tSU;STO  
tBUF  
Set-up time for a repeated START condition  
Data hold time  
3.45  
0.9  
f
SCL > 100 kHz  
0
fSCL 100 kHz  
fSCL > 100 kHz  
fSCL 100 kHz  
fSCL > 100 kHz  
fSCL 100 kHz  
fSCL > 100 kHz  
250  
100  
4.0  
0.6  
4.7  
1.3  
Data setup time  
Setup time for STOP condition  
Bus free time between a STOP and START  
condition  
Notes: 1. In ATmega32, this parameter is characterized and not 100ꢀ tested.  
2. Required only for fSCL > 100 kHz.  
3. Cb = capacitance of one bus line in pF.  
4. fCK = CPU clock frequency  
290  
ATmega32(L)  
2503J–AVR–10/06  
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