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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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8-bit Timer/Counter2 Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module.  
The main features are:  
Single Compare unit Counter  
Clear Timer on Compare Match (Auto Reload)  
Glitch-free, Phase Correct Pulse Width Modulator (PWM)  
with PWM and  
Asynchronous  
Operation  
Frequency Generator  
10-bit Clock Prescaler  
Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)  
Allows clocking from External 32 kHz Watch Crystal Independent of the I/O Clock  
Overview  
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 53. For the  
actual placement of I/O pins, refer to “Pinout ATmega32” on page 2. CPU accessible I/O  
Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O  
Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on  
page 125.  
Figure 53. 8-bit Timer/Counter Block Diagram  
TCCRn  
count  
TOVn  
(Int.Req.)  
clear  
Control Logic  
TOP  
direction  
clkTn  
TOSC1  
TOSC2  
BOTTOM  
T/C  
Oscillator  
Prescaler  
Timer/Counter  
TCNTn  
= 0  
= 0xFF  
clkI/O  
OCn  
OCn  
(Int.Req.)  
Waveform  
Generation  
=
OCRn  
clkI/O  
Synchronized Status flags  
Synchronization Unit  
clkASY  
Status flags  
ASSRn  
asynchronous mode  
select (ASn)  
Registers  
The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers.  
Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag  
Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask  
Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are  
shared by other timer units.  
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously  
clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous  
operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select  
logic block controls which clock source the Timer/Counter uses to increment (or decre-  
ment) its value. The Timer/Counter is inactive when no clock source is selected. The  
output from the Clock Select logic is referred to as the timer clock (clkT2).  
114  
ATmega32(L)  
2503J–AVR–10/06  
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