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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第106页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第107页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第108页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第109页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第111页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第112页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第113页浏览型号ATMEGA32L-8AUR的Datasheet PDF文件第114页  
Timer/Counter1 Control  
Register B – TCCR1B  
Bit  
7
ICNC1  
R/W  
0
6
ICES1  
R/W  
0
5
4
WGM13  
R/W  
0
3
WGM12  
R/W  
0
2
CS12  
R/W  
0
1
CS11  
R/W  
0
0
CS10  
R/W  
0
TCCR1B  
Read/Write  
Initial Value  
R
0
• Bit 7 – ICNC1: Input Capture Noise Canceler  
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise  
Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter  
function requires four successive equal valued samples of the ICP1 pin for changing its  
output. The Input Capture is therefore delayed by four Oscillator cycles when the Noise  
Canceler is enabled.  
• Bit 6 – ICES1: Input Capture Edge Select  
This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a cap-  
ture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as  
trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the  
capture.  
When a capture is triggered according to the ICES1 setting, the counter value is copied  
into the Input Capture Register (ICR1). The event will also set the Input Capture Flag  
(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is  
enabled.  
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in  
the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently  
the Input Capture function is disabled.  
• Bit 5 – Reserved Bit  
This bit is reserved for future use. For ensuring compatibility with future devices, this bit  
must be written to zero when TCCR1B is written.  
• Bit 4:3 – WGM13:2: Waveform Generation Mode  
See TCCR1A Register description.  
• Bit 2:0 – CS12:0: Clock Select  
The three Clock Select bits select the clock source to be used by the Timer/Counter, see  
Figure 49 and Figure 50.  
Table 48. Clock Select Bit Description  
CS12  
CS11  
CS10  
Description  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
No clock source (Timer/Counter stopped).  
clkI/O/1 (No prescaling)  
clkI/O/8 (From prescaler)  
clkI/O/64 (From prescaler)  
clkI/O/256 (From prescaler)  
110  
ATmega32(L)  
2503J–AVR–10/06  
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