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ATMEGA32L-8AUR 参数 Datasheet PDF下载

ATMEGA32L-8AUR图片预览
型号: ATMEGA32L-8AUR
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 8MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44]
分类和应用: 闪存微控制器
文件页数/大小: 347 页 / 3171 K
品牌: ATMEL [ ATMEL ]
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Table 45. Compare Output Mode, Fast PWM(1)  
COM1A1/COM1B1  
COM1A0/COM1B0  
Description  
0
0
Normal port operation, OC1A/OC1B  
disconnected.  
0
1
WGM13:0 = 15: Toggle OC1A on Compare  
Match, OC1B disconnected (normal port  
operation).  
For all other WGM13:0 settings, normal port  
operation, OC1A/OC1B disconnected.  
1
1
0
1
Clear OC1A/OC1B on compare match, set  
OC1A/OC1B at BOTTOM,  
(non-inverting mode)  
Set OC1A/OC1B on compare match, clear  
OC1A/OC1B at BOTTOM,  
(inverting mode)  
Note:  
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is  
set. In this case the compare match is ignored, but the set or clear is done at BOT-  
TOM. See “Fast PWM Mode” on page 99. for more details.  
Table 46 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the  
phase correct or the phase and frequency correct, PWM mode.  
Table 46. Compare Output Mode, Phase Correct and Phase and Frequency Correct  
PWM (1)  
COM1A1/COM1B1  
COM1A0/COM1B0  
Description  
0
0
Normal port operation, OC1A/OC1B  
disconnected.  
0
1
WGM13:0 = 9 or 14: Toggle OC1A on  
Compare Match, OC1B disconnected (normal  
port operation).  
For all other WGM13:0 settings, normal port  
operation, OC1A/OC1B disconnected.  
1
1
0
1
Clear OC1A/OC1B on compare match when  
up-counting. Set OC1A/OC1B on compare  
match when downcounting.  
Set OC1A/OC1B on compare match when up-  
counting. Clear OC1A/OC1B on compare  
match when downcounting.  
Note:  
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is  
set. See “Phase Correct PWM Mode” on page 101. for more details.  
• Bit 3 – FOC1A: Force Output Compare for Compare unit A  
• Bit 2 – FOC1B: Force Output Compare for Compare unit B  
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM  
mode. However, for ensuring compatibility with future devices, these bits must be set to  
zero when TCCR1A is written when operating in a PWM mode. When writing a logical  
one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform  
Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits  
setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is  
the value present in the COM1x1:0 bits that determine the effect of the forced compare.  
108  
ATmega32(L)  
2503J–AVR–10/06  
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