ATmega640/1280/1281/2560/2561
Figure 134. General Port Pin Schematic Diagram
See Boundary-scan
Description for Details!
PUExn
PUD
Q
D
DDxn
Q CLR
WDx
RDx
RESET
OCxn
Q
D
Pxn
PORTxn
ODxn
Q CLR
WRx
RRx
IDxn
RESET
SLEEP
SYNCHRONIZER
RPx
D
Q
D
L
Q
Q
PINxn
Q
CLK I/O
PUD:
PULLUP DISABLE
WDx:
RDx:
WRITE DDRx
PUExn:
OCxn:
ODxn:
IDxn:
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
READ DDRx
WRx:
RRx:
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
RPx:
SLEEP:
CLK I/O :
Scanning the RESET Pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active
high logic for High Voltage Parallel programming. An observe-only cell as shown in Fig-
ure 135 is inserted for the 5V reset signal.
Figure 135. Observe-only Cell
To
Next
ShiftDR
Cell
From System Pin
To System Logic
FF1
0
1
D
Q
From
ClockDR
Previous
Cell
307
2549A–AVR–03/05
ATMEL [ ATMEL ]
