ATmega640/1280/1281/2560/2561
A change of the COMnx1:0 bits state will have effect at the first compare match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect
by using the FOCnx strobe bits.
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and
Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the out-
put should be set, cleared or toggle at a compare match (See “Compare Match Output
Unit” on page 146.)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 154.
Normal Mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and
then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Over-
flow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero.
The TOVn Flag in this case behaves like a 17th bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOVn
Flag, the timer resolution can be increased by software. There are no special cases to
consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maxi-
mum interval between the external events must not exceed the resolution of the counter.
If the interval between events are too long, the timer overflow interrupt or the prescaler
must be used to extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using
the Output Compare to generate waveforms in Normal mode is not recommended,
since this will occupy too much of the CPU time.
Clear Timer on Compare
Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn
Register are used to manipulate the counter resolution. In CTC mode the counter is
cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0
= 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the
counter, hence also its resolution. This mode allows greater control of the compare
match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 54. The counter value
(TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then
counter (TCNTn) is cleared.
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2549A–AVR–03/05
ATMEL [ ATMEL ]
