欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA2560 参数 Datasheet PDF下载

ATMEGA2560图片预览
型号: ATMEGA2560
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器与256K字节的系统内可编程闪存 [8- BIT Microcontroller with 256K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 407 页 / 2985 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA2560的Datasheet PDF文件第132页浏览型号ATMEGA2560的Datasheet PDF文件第133页浏览型号ATMEGA2560的Datasheet PDF文件第134页浏览型号ATMEGA2560的Datasheet PDF文件第135页浏览型号ATMEGA2560的Datasheet PDF文件第137页浏览型号ATMEGA2560的Datasheet PDF文件第138页浏览型号ATMEGA2560的Datasheet PDF文件第139页浏览型号ATMEGA2560的Datasheet PDF文件第140页  
Figure 49. 16-bit Timer/Counter Block Diagram(1)  
Count  
TOVn  
(Int.Req.)  
Clear  
Control Logic  
Clock Select  
Direction  
TCLK  
Edge  
Detector  
Tn  
TOP BOTTOM  
( From Prescaler )  
Timer/Counter  
TCNTn  
=
= 0  
OCFnA  
(Int.Req.)  
Waveform  
Generation  
OCnA  
OCnB  
OCnC  
=
OCRnA  
OCFnB  
Fixed  
TOP  
Values  
(Int.Req.)  
Waveform  
Generation  
=
OCRnB  
OCFnC  
(Int.Req.)  
Waveform  
Generation  
=
OCRnC  
( From Analog  
Comparator Ouput )  
ICFn (Int.Req.)  
Edge  
Detector  
Noise  
Canceler  
ICRn  
ICPn  
TCCRnA  
TCCRnB  
TCCRnC  
Note:  
1. Refer to Figure 1 on page 2, Table 38 on page 89, and Table 44 on page 93 for  
Timer/Counter1 and 3 and 3 pin placement and description.  
Registers  
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Cap-  
ture Register (ICRn) are all 16-bit registers. Special procedures must be followed when  
accessing the 16-bit registers. These procedures are described in the section “Access-  
ing 16-bit Registers” on page 137. The Timer/Counter Control Registers (TCCRnA/B/C)  
are 8-bit registers and have no CPU access restrictions. Interrupt requests (shorten as  
Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts  
are individually masked with the Timer Interrupt Mask Register (TIMSKn). TIFRn and  
TIMSKn are not shown in the figure since these registers are shared by other timer  
units.  
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock  
source on the Tn pin. The Clock Select logic block controls which clock source and edge  
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is  
inactive when no clock source is selected. The output from the clock select logic is  
referred to as the timer clock (clk ).  
n
T
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the  
Timer/Counter value at all time. The result of the compare can be used by the Waveform  
Generator to generate a PWM or variable frequency output on the Output Compare pin  
(OCnA/B/C). See “Output Compare Units” on page 144.. The compare match event will  
136  
ATmega640/1280/1281/2560/2561  
2549A–AVR–03/05  
 复制成功!