Table 72 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to
phase correct PWM mode.
Table 75. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
Description
0
0
1
0
1
0
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
1
1
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-
rect PWM Mode” on page 124 for more details.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
what type of waveform generation to be used, see Table 76. Modes of operation sup-
ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare
Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see
“Modes of Operation” on page 147).
Table 76. Waveform Generation Mode Bit Description
Timer/Counter
Mode of
Update of
OCRx at
TOV Flag
Mode WGM2 WGM1 WGM0 Operation
TOP
0xFF
0xFF
Set on(1)(2)
0
1
0
0
0
0
0
1
Normal
Immediate
TOP
MAX
PWM, Phase
Correct
BOTTOM
2
3
4
5
0
0
1
1
1
1
0
0
0
1
0
1
CTC
OCRA Immediate
MAX
MAX
Fast PWM
Reserved
0xFF
–
TOP
–
–
PWM, Phase
Correct
OCRA
TOP
BOTTOM
6
7
1
1
1
1
0
1
Reserved
Fast PWM
–
–
–
OCRA
TOP
TOP
Notes: 1. MAX
= 0xFF
2. BOTTOM = 0x00
130
ATmega640/1280/1281/2560/2561
2549A–AVR–03/05
ATMEL [ ATMEL ]
