ATmega640/1280/1281/2560/2561
Figure 41. Compare Match Output Unit, Schematic
COMnx1
Waveform
Generator
COMnx0
FOCn
D
Q
1
0
OCnx
Pin
OCnx
D
Q
PORT
D
Q
DDR
clkI/O
The general I/O port function is overridden by the Output Compare (OC0x) from the
Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin
direction (input or output) is still controlled by the Data Direction Register (DDR) for the
port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as
output before the OC0x value is visible on the pin. The port override function is indepen-
dent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before
the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain
modes of operation. See “8-bit Timer/Counter Register Description” on page 128.
Compare Output Mode and
Waveform Generation
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no
action on the OC0x Register is to be performed on the next Compare Match. For com-
pare output actions in the non-PWM modes refer to Table 70 on page 128. For fast
PWM mode, refer to Table 71 on page 128, and for phase correct PWM refer to Table
72 on page 129.
A change of the COM0x1:0 bits state will have effect at the first Compare Match after
the bits are written. For non-PWM modes, the action can be forced to have immediate
effect by using the FOC0x strobe bits.
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare
pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and
Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COM0x1:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the out-
put should be set, cleared, or toggled at a Compare Match (See “Compare Match
Output Unit” on page 146.).
For detailed timing information see “Timer/Counter Timing Diagrams” on page 126.
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2549A–AVR–03/05
ATMEL [ ATMEL ]
