ATmega8U2/16U2/32U2
Table 16-4. Waveform Generation Mode Bit Description(1)
WGMn2
(CTCn)
WGMn1
WGMn0
Timer/Counter Mode of
Update of
OCRnx at
TOVn Flag
Set on
Mode
WGMn3
(PWMn1) (PWMn0) Operation
TOP
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal
0xFFFF
0x00FF
0x01FF
0x03FF
OCRnA
0x00FF
0x01FF
0x03FF
Immediate
TOP
MAX
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
BOTTOM
BOTTOM
BOTTOM
MAX
TOP
TOP
Immediate
TOP
Fast PWM, 8-bit
TOP
Fast PWM, 9-bit
TOP
TOP
Fast PWM, 10-bit
TOP
TOP
PWM, Phase and Frequency
Correct
8
9
1
1
0
0
0
0
0
1
ICRn
BOTTOM
BOTTOM
BOTTOM
BOTTOM
PWM, Phase and Frequency
Correct
OCRnA
10
11
12
13
14
15
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
PWM, Phase Correct
PWM, Phase Correct
CTC
ICRn
OCRnA
ICRn
–
TOP
TOP
Immediate
–
BOTTOM
BOTTOM
MAX
(Reserved)
–
Fast PWM
ICRn
OCRnA
TOP
TOP
TOP
Fast PWM
TOP
Note:
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
132
7799D–AVR–11/10
ATMEL [ ATMEL ]
