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ATMEGA16M1-15MZ 参数 Datasheet PDF下载

ATMEGA16M1-15MZ图片预览
型号: ATMEGA16M1-15MZ
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQCC32,]
分类和应用: 微控制器
文件页数/大小: 27 页 / 689 K
品牌: ATMEL [ ATMEL ]
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2.3  
Pin Descriptions  
2.3.1  
VCC  
Digital supply voltage.  
2.3.2  
2.3.3  
GND  
Ground.  
Port B (PB7..PB0)  
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The  
Port B output buffers have symmetrical drive characteristics with both high sink and source  
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up  
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,  
even if the clock is not running.  
Port B also serves the functions of various special features of the ATmega16/32/64/M1/C1.  
2.3.4  
2.3.5  
2.3.6  
Port C (PC7..PC0)  
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The  
Port C output buffers have symmetrical drive characteristics with both high sink and source  
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up  
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,  
even if the clock is not running.  
Port C also serves the functions of special features of the ATmega16/32/64/M1/C1.  
Port D (PD7..PD0)  
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The  
Port D output buffers have symmetrical drive characteristics with both high sink and source  
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up  
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,  
even if the clock is not running.  
Port D also serves the functions of various special features of the ATmega16/32/64/M1/C1.  
Port E (PE2..0) RESET/ XTAL1/ XTAL2  
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The  
Port E output buffers have symmetrical drive characteristics with both high sink and source  
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up  
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,  
even if the clock is not running.  
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical char-  
acteristics of PE0 differ from those of the other pins of Port E.  
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin  
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.  
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscil-  
lator amplifier and input to the internal clock operating circuit.  
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting  
Oscillator amplifier.  
10  
Atmel ATmega16/32/64/M1/C1  
7647ES–AVR–07/12  
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