Atmel ATmega16/32/64/M1/C1
Mnemonics
Operands
Description
Operation
Flags
#Clocks
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ←PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
P,b
P,b
Rd
Rd
Rd
Rd
Rd
Rd
s
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ←1
None
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O(P,b) ←0
None
LSL
Rd(n+1) ←Rd(n), Rd(0) ←0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rd(n) ←Rd(n+1), Rd(7) ←0
Z,C,N,V
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(0)←C,Rd(n+1)←Rd(n),C←Rd(7)
Z,C,N,V
Rd(7)←C,Rd(n)←Rd(n+1),C←Rd(0)
Z,C,N,V
Rd(n) ←Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ←1
SREG(s) ←0
T ←Rr(b)
Rd(b) ←T
C ←1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ←0
Set Negative Flag
N ←1
Clear Negative Flag
Set Zero Flag
N ←0
Z ←1
Clear Zero Flag
Z ←0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ←1
I
CLI
I ←0
I
SES
CLS
SEV
CLV
SET
CLT
S ←1
S
S ←0
S
V ←1
V
V ←0
V
T ←1
T
Clear T in SREG
T ←0
T
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ←1
H ←0
H
H
1
1
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ←Rr
Rd+1:Rd ←Rr+1:Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Load Immediate
Rd ←K
Rd ←(X)
Rd, X
Load Indirect
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ←(X), X ←X + 1
X ←X - 1, Rd ←(X)
Rd ←(Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ←(Y), Y ←Y + 1
Y ←Y - 1, Rd ←(Y)
Rd ←(Y + q)
Rd ←(Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ←(Z), Z ←Z+1
Z ←Z - 1, Rd ←(Z)
Rd ←(Z + q)
Rd ←(k)
LD
LDD
LDS
ST
X, Rr
(X) ←Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ←Rr, X ←X + 1
X ←X - 1, (X) ←Rr
(Y) ←Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ←Rr, Y ←Y + 1
Y ←Y - 1, (Y) ←Rr
(Y + q) ←Rr
ST
STD
ST
(Z) ←Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ←Rr, Z ←Z + 1
Z ←Z - 1, (Z) ←Rr
(Z + q) ←Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ←Rr
R0 ←(Z)
Rd, Z
Rd ←(Z)
Rd, Z+
Rd ←(Z), Z ←Z+1
(Z) ←R1:R0
Rd, P
P, Rr
Rr
Rd ←P
1
1
2
2
OUT
PUSH
POP
Out Port
P ←Rr
Push Register on Stack
Pop Register from Stack
STACK ←Rr
Rd ←STACK
Rd
13
7647ES–AVR–07/12
ATMEL [ ATMEL ]
