ATmega169P
Table 26-4. Fuse High Byte
Fuse High Byte
OCDEN(4)
Bit No
Description
Enable OCD
Enable JTAG
Default Value
7
6
1 (unprogrammed, OCD disabled)
0 (programmed, JTAG enabled)
JTAGEN(5)
Enable Serial Program and Data
Downloading
0 (programmed, SPI prog.
enabled)
SPIEN(1)
WDTON(3)
EESAVE
5
4
3
Watchdog Timer always on
1 (unprogrammed)
EEPROM memory is preserved
through the Chip Erase
1 (unprogrammed, EEPROM not
preserved)
Select Boot Size (see Table 25-6
for details)
BOOTSZ1
2
0 (programmed)(2)
Select Boot Size (see Table 25-6
for details)
BOOTSZ0
BOOTRST
1
0
0 (programmed)(2)
1 (unprogrammed)
Select Reset Vector
Note:
1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 25-6 on page 291
for details.
3. See ”WDTCR – Watchdog Timer Control Register” on page 54 for details.
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sleep modes. This may increase the power consumption.
5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This
to avoid static current at the TDO pin in the JTAG interface.
Table 26-5. Fuse Low Byte
Fuse Low Byte
CKDIV8(4)
CKOUT(3)
SUT1
Bit No
Description
Default Value
7
6
5
4
3
2
1
0
Divide clock by 8
Clock output
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)(1)
0 (programmed)(1)
0 (programmed)(2)
0 (programmed)(2)
1 (unprogrammed)(2)
0 (programmed)(2)
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
Note:
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
See Table 9-1 on page 47 for details.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 7-9 on
page 34 for details.
3. The CKOUT Fuse allow the system clock to be output on PORTE7. See ”Clock Output Buffer”
on page 36 for details.
4. See ”System Clock Prescaler” on page 36 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
297
8018A–AVR–03/06
ATMEL [ ATMEL ]
