Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM
mode
Table 59. Compare Output Mode, Fast PWM
COMnA1/COMnB1/
COMnC1
COMnA0/COMnB0/
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC
disconnected.
0
1
WGMn3:0 = 15: Toggle OCnA on Compare
Match, OCnB/OCnC disconnected (normal
port operation).
For all other WGMn settings, normal port
operation, OCnA/OCnB/OCnC
disconnected.
1
1
0
1
Clear OCnA/OCnB/OCnC on compare
match, set OCnA/OCnB/OCnC at BOTTOM,
(non-inverting mode)
Set OCnA/OCnB/OCnC on compare match,
clear OCnA/OCnB/OCnC at BOTTOM,
(inverting mode)
Note:
A
special
case
occurs
when
OCRnA/OCRnB/OCRnC
equals
TOP
and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at BOTTOM. See “Fast PWM Mode” on page 125. for more details.
Table 59 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase cor-
rect and frequency correct PWM mode.
Table 60. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
COMnA1/COMnB1/
COMnC1
COMnA0/COMnB0/
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC
disconnected.
0
1
WGMn3:0 = 9 or 11: Toggle OCnA on
Compare Match, OCnB/OCnC disconnected
(normal port operation).
For all other WGMn settings, normal port
operation, OCnA/OCnB/OCnC
disconnected.
1
1
0
1
Clear OCnA/OCnB/OCnC on compare
match when up-counting. Set
OCnA/OCnB/OCnC on compare match
when downcounting.
Set OCnA/OCnB/OCnC on compare match
when up-counting. Clear
OCnA/OCnB/OCnC on compare match
when downcounting.
Note:
A
special
case
occurs
when
OCRnA/OCRnB/OCRnC
equals
TOP
and
COMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode” on page 127. for more
details.
134
ATmega128(L)
2467P–AVR–08/07
ATMEL [ ATMEL ]
