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ATMEGA2560-16AU-SL383 参数 Datasheet PDF下载

ATMEGA2560-16AU-SL383图片预览
型号: ATMEGA2560-16AU-SL383
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, MS-026AED, TQFP-100]
分类和应用: 时钟微控制器
文件页数/大小: 448 页 / 7518 K
品牌: ATMEL [ ATMEL ]
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ATmega640/1280/1281/2560/2561  
Figure 28-1. Reset Register  
To  
TDO  
From Other Internal and  
External Reset Sources  
From  
TDI  
Internal reset  
D
Q
ClockDR · AVR_RESET  
28.3.4  
Boundary-scan Chain  
The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-  
ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having  
off-chip connections.  
See “Boundary-scan Chain” on page 306 for a complete description.  
28.4 Boundary-scan Specific JTAG Instructions  
The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the  
JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction  
is not implemented, but all outputs with tri-state capability can be set in high-impedant state by  
using the AVR_RESET instruction, since the initial state for all port pins is tri-state.  
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.  
The OPCODE for each instruction is shown behind the instruction name in hex format. The text  
describes which Data Register is selected as path between TDI and TDO for each instruction.  
28.4.1  
EXTEST; 0x0  
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing  
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output  
Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip  
connections, the interface between the analog and the digital logic is in the scan chain. The con-  
tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR-  
Register is loaded with the EXTEST instruction.  
The active states are:  
Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.  
Shift-DR: The Internal Scan Chain is shifted by the TCK input.  
Update-DR: Data from the scan chain is applied to output pins.  
28.4.2  
IDCODE; 0x1  
Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register  
consists of a version number, a device number and the manufacturer code chosen by JEDEC.  
This is the default instruction after power-up.  
305  
2549L–AVR–08/07  
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