Figure 26-1. Analog to Digital Converter Block Schematic
ADC CONVERSION
COMPLETE IRQ
INTERRUPT
FLAGS
ADTS[2:0]
8-BIT DATABUS
15
ADC DATA REGISTER
(ADCH/ADCL)
0
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL & STATUS
REGISTER B (ADCSRB)
ADC CTRL & STATUS
REGISTER A (ADCSRA)
TRIGGER
SELECT
START
PRESCALER
MUX DECODER
CONVERSION LOGIC
AVCC
INTERNAL
REFERENCE
(1.1V/2.56V)
-
AREF
10-bit DAC
+
SAMPLE & HOLD
COMPARATOR
ADC[2:0]
-
ADC[10:8]
+
GAIN
R
AMPLIFIE
ADC[15:0]
ADC
MULTIPLEXER
OUTPUT
BANDGAP (1.1V)
REFERENCE
GND
26.2 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-
mation. The minimum value represents GND and the maximum value represents the voltage on
the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V or 2.56V reference voltage
may be connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The
internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to
improve noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX and ADCSRB. Any of
the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as
276
ATmega640/1280/1281/2560/2561
2549L–AVR–08/07
ATMEL [ ATMEL ]
