ATmega640/1280/1281/2560/2561
24. 2-wire Serial Interface
24.1 Features
• Simple yet Powerful and Flexible Communication Interface, only two Bus Lines needed
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition Causes Wake-up When AVR is in Sleep Mode
24.2 2-wire Serial Interface Bus Definition
The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 2. TWI Bus Interconnection
VCC
Device 1
Device 3
R1
R2
Device 2
Device n
........
SDA
SCL
24.2.1
TWI Terminology
The following definitions are frequently encountered in this section.
Table 4. TWI Terminology
Term
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
Master
Slave
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
Transmitter
Receiver
241
2549L–AVR–08/07
ATMEL [ ATMEL ]
