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ATMEGA2560-16AU-SL383 参数 Datasheet PDF下载

ATMEGA2560-16AU-SL383图片预览
型号: ATMEGA2560-16AU-SL383
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 16MHz, CMOS, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, MS-026AED, TQFP-100]
分类和应用: 时钟微控制器
文件页数/大小: 448 页 / 7518 K
品牌: ATMEL [ ATMEL ]
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Figure 20-6. Output Compare Unit, Block Diagram  
DATA BUS  
OCRnx  
TCNTn  
=
(8-bit Comparator )  
OCFnx (Int.Req.)  
top  
bottom  
FOCn  
Waveform Generator  
OCnx  
WGMn1:0  
COMnX1:0  
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)  
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double  
buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare  
Register to either top or bottom of the counting sequence. The synchronization prevents the  
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.  
The OCR2x Register access may seem complex, but this is not case. When the double buffering  
is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is dis-  
abled the CPU will access the OCR2x directly.  
20.5.1  
Force Output Compare  
In non-PWM waveform generation modes, the match output of the comparator can be forced by  
writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the  
OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare  
match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or  
toggled).  
20.5.2  
20.5.3  
Compare Match Blocking by TCNT2 Write  
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the  
next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initial-  
ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is  
enabled.  
Using the Output Compare Unit  
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock  
cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,  
independently of whether the Timer/Counter is running or not. If the value written to TCNT2  
equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform  
generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is  
downcounting.  
182  
ATmega640/1280/1281/2560/2561  
2549L–AVR–08/07  
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