AT90PWM2/3/2B/3B
26.6 SPI Timing Characteristics
See Figure 26-3 and Figure 26-4 for details.
Table 26-4. SPI Timing Parameters
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Mode
Min.
Typ.
Max.
1
2
Master
Master
Master
Master
Master
Master
Master
Master
Slave
See Table 17-4
50% duty cycle
3
3.6
10
4
5
Hold
10
6
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low (1)
Rise/Fall time
Setup
0.5 • tsck
10
7
8
10
9
15
ns
10
11
12
13
14
15
16
17
18
Slave
4 • tck
2 • tck
Slave
Slave
1.6
Slave
10
tck
Hold
Slave
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
Slave
15
10
Slave
20
Slave
Slave
2 • tck
Note:
In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK >12 MHz
Figure 26-3. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
4
5
3
MISO
(Data Input)
MSB
...
LSB
7
8
MOSI
(Data Output)
MSB
...
LSB
303
4317J–AVR–08/10
ATMEL [ ATMEL ]
