AT90PWM2/3/2B/3B
Table 25-14. Parallel Programming Characteristics, VCC = 5V 10% (Continued)
Symbol
tXLPH
Parameter
Min
0
Typ
Max
Units
ns
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
tPLXH
150
67
150
67
67
67
67
150
0
ns
tBVPH
tPHPL
ns
ns
tPLBX
ns
tWLBX
tPLWL
tBVWL
tWLWH
tWLRL
tWLRH
tWLRH_CE
tXLOL
ns
ns
ns
WR Pulse Width Low
ns
WR Low to RDY/BSY Low
WR Low to RDY/BSY High(1)
WR Low to RDY/BSY High for Chip Erase(2)
XTAL1 Low to OE Low
1
4.5
9
μs
ms
ms
ns
3.7
7.5
0
tBVDV
tOLDV
tOHDZ
BS1 Valid to DATA valid
OE Low to DATA Valid
0
250
250
250
ns
ns
OE High to DATA Tri-stated
ns
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.
25.9 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 25-13 on page 284, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
293
4317J–AVR–08/10
ATMEL [ ATMEL ]
