AT89S52-24SI 参数 Datasheet PDF下载

AT89S52

Table 5-3.

AUXR

AUXR: Auxiliary Register

Address = 8EH

Not Bit Addressable

–

Bit

7

–

6

–

5

WDIDLE

4

DISRTO

3

–

2

–

1

DISALE

0

Reset Value = XXX00XX0B

–

DISALE

Reserved for future expansion

Disable/Enable ALE

DISALE

0

1

Operating Mode

ALE is emitted at a constant rate of 1/6 the oscillator frequency

ALE is active only during a MOVX or MOVC instruction

DISRTO

Disable/Enable Reset out

DISRTO

0

1

Reset pin is driven High after WDT times out

Reset pin is input only

WDIDLE

Disable/Enable WDT in IDLE mode

WDIDLE

0

1

WDT continues to count in IDLE mode

WDT halts counting in IDLE mode

Dual Data Pointer Registers:

To facilitate accessing both internal and external data memory, two banks of 16-bit Data

Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1

selects DP0 and DPS = 1 selects DP1. The user should

ALWAYS

initialize the DPS bit to the appropriate value before

accessing the respective Data Pointer Register.

Power Off Flag:

The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power

up. It can be set and rest under software control and is not affected by reset.

Table 5-4.

AUXR1

AUXR1: Auxiliary Register 1

Address = A2H

Not Bit Addressable

–

Bit

7

–

6

–

5

–

4

–

3

–

2

–

1

DPS

0

Reset Value = XXXXXXX0B

–

DPS

Reserved for future expansion

Data Pointer Register Select

DPS

0

1

Selects DPTR Registers DP0L, DP0H

Selects DPTR Registers DP1L, DP1H

9

1919C–MICRO–3/05