Figure 1-2. Block Diagram
WP
Flash Memory Array
Page (512-/528-bytes)
Buffer 1 (512-/528-bytes)
Buffer 2 (512-/528-bytes)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O Interface
SI
SO
2.
Memory Array
To provide optimal flexibility, the AT45DB321D memory array is divided into three levels of granularity comprising sectors,
blocks, and pages. The
illustrates the breakdown of each level, and details the number of
pages per sector and block. All program operations to the DataFlash device occur on a page-by-page basis. The erase
operations can be performed at the chip, sector, block, or page level.
Figure 2-1. Memory Architecture Diagram
Sector Architecture
SECTOR 0a = 8 Pages
4,096-/4,224-bytes
Block Architecture
SECTOR 0a
BLOCK 0
BLOCK 1
Page Architecture
8 Pages
PAGE 0
PAGE 1
SECTOR 0b = 120 Pages
61,440-/63,360-bytes
SECTOR 0b
BLOCK 2
BLOCK 0
PAGE 6
BLOCK 62
BLOCK 63
PAGE 7
PAGE 8
PAGE 9
SECTOR 1 = 128 Pages
65,536-/67,584-bytes
SECTOR 2 = 128 Pages
65,536-/67,584-bytes
SECTOR 1
BLOCK 65
BLOCK 1
BLOCK 64
PAGE 14
PAGE 15
BLOCK 126
BLOCK 127
BLOCK 128
PAGE 16
PAGE 17
PAGE 18
SECTOR 62 = 128 Pages
65,536-/67,584-bytes
BLOCK 129
SECTOR 63 = 128 Pages
65,536-/67,586-bytes
BLOCK 1,022
BLOCK 1,023
PAGE 8,190
PAGE 8,191
Block = 4,096-/4,224-bytes
Page = 512-/528-bytes
Atmel AT45DB321D
3597Q–DFLASH–6/11
4
ATMEL [ ATMEL CORPORATION ]
