The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a
page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the
next page, with no delays incurred during the page boundary crossover (the crossover from the end of one page to the
beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at
the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping
around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read
operation and tri-state the output pin (SO). The maximum SCK frequency allowable for the continuous array read is defined by
the f
CAR1
specification. The continuous array read bypasses both data buffers and leaves the contents of the buffers unchanged.
4.3
Continuous Array Read (Low Frequency Mode: 03H): Up to 33MHz
This command can be used with the serial interface to read the main memory array sequentially without a dummy byte up to the
maximum frequency specified by f
CAR2
. To perform a continuous read array with the page size set to 528 bytes, the CS must
first be asserted, and then a 03H opcode must be clocked into the device, followed by three address bytes (which comprise the
24-bit page and byte address sequence). The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify which page of
the main memory array to read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify the starting byte
address within the page. To perform a continuous read with the page size set to 512 bytes, the 03H opcode must be clocked
into the device, followed by three address bytes (A21 - A0). Following the address bytes, additional clock pulses on the SCK pin
will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end of a
page in the main memory is reached during a continuous array read, the device will continue reading at the beginning of the
next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning
of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the
beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around
from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The continuous array read bypasses both data buffers and leaves the contents of the buffers
unchanged.
4.4
Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 8,192 pages in the main memory, bypassing
both of the data buffers and leaving the contents of the buffers unchanged. To start a page read from the standard DataFlash
page size (528 bytes), an opcode of D2H must be clocked into the device, followed by three address bytes (which comprise the
24-bit page and byte address sequence) and four don’t care bytes. The first 13 bits (PA12 - PA0) of the 23-bit address
sequence specify the page in main memory to be read, and the last 10 bits (BA9 - BA0) of the 23-bit address sequence specify
the starting byte address within that page. To start a page read from the binary page size (512 bytes), the D2H opcode must be
clocked into the device, followed by three address bytes and four don’t care bytes. The first 13 bits (A21 - A9) of the 22-bit
sequence specify which page of the main memory array to read, and the last 9 bits (A8 - A0) of the 22-bit address sequence
specify the starting byte address within the page. The don’t care bytes that follow the address bytes are sent to initialize the
read operation. Following the don’t care bytes, additional pulses on SCK result in data being output on the SO (serial output)
pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of
data. When the end of a page in main memory is reached, the device will continue reading back at the beginning of the same
page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the main memory page read is defined by the f
SCK
specification. The main memory page read
bypasses both data buffers and leaves the contents of the buffers unchanged.
4.5
Buffer Read
The SRAM data buffers can be accessed independently of the main memory array, and utilizing the buffer read command
allows data to be sequentially read directly from the buffers. Four opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer
2, can be used for the buffer read command. The use of each opcode depends on the maximum SCK frequency that will be
used to read data from the buffer. The D4H and D6H opcodes can be used at any SCK frequency, up to the maximum specified
by f
CAR1
. The D1H and D3H opcodes can be used for lower frequency read operations, up to the maximum specified by f
CAR2
.
To perform a buffer read from the standard DataFlash buffer (528 bytes), the opcode must be clocked into the device, followed
by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0). To perform a buffer read from
the binary buffer (512 bytes), the opcode must be clocked into the device, followed by three address bytes comprised of 15
don’t care bits and 9 buffer address bits (BFA8 - BFA0). Following the address bytes, one don’t care byte must be clocked in to
initialize the read operation. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
byte, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the
buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO).
Atmel AT45DB321D
3597Q–DFLASH–6/11
6
ATMEL [ ATMEL CORPORATION ]
