AT25080A/160A/320A/640A
3. Functional Description
The AT25080A/160A/320A/640A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in
All instructions, addresses, and data are trans-
ferred with the MSB first and start with a high-to-low CS transition.
Table 3-1.
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction Set for the AT25080A/160A/320A/640A
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Instruction Name
WRITE ENABLE (WREN):
The device will power up in the write disable state when V
CC
is
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI):
To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR):
The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protec-
tion employed. These bits are set by using the WRSR instruction.
Table 3-2.
Bit 7
WPEN
Status Register Format
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
9
3347L–SEEPR–06/07
ATMEL [ ATMEL CORPORATION ]
