AD7322
Preliminary Technical Data
CS
when the
signal is brought high the addressed register may
SERIAL INTERFACE
or may not be updated. Data is clocked into the AD7322 on the
SCLK falling edge. The three MSB on the DIN line are decoded
to select which register is being addressed. The Control Register
is an eleven bit register, if the control register is addressed by the
three MSB, the data on the DIN line will be loaded into the
Control on the 1ꢁth SCLK falling edge. If the Range registers is
addressed the data on the DIN line will be loaded into the
addressed register on the 11th SCLK falling edge.
Figure 14 shows the timing diagram for the serial interface of
the AD7322. The serial clock applied to the SCLK pin provides
the conversion clock and also controls the transfer of
information to and from the AD7322 during a conversion.
CS
The
signal initiates the data transfer and the conversion
CS
process. The falling edge of
puts the track-and-hold into
hold mode, take the bus out of three-state and the analog input
signal is sampled at this point. Once the conversion is initiated
it will require 16 SCLK cycles to complete.
Conversion data is clocked out of the AD7322 on each SCLK
falling edge. Data on the DOUT line will consist of two leading
zeros, a channel identifier bit, a Sign bit and the 12-bit
conversion result. The channel identifier bit is used to indicate
which channel the conversion result corresponds to.
The track-and-hold will go back into track on the 1ꢁth SCLK
falling edge. On the sixteenth SCLK falling edge, the DOUT line
will return to three-state. If the rising edge of
CS
occurs before
16 SCLK cycles have elapsed, the conversion will be terminated,
the DOUT line will return to three-state, and depending on
Figure 14. Serial Interface timing Diagram (Control register write)
Rev. PrE | Page 17 of 18
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