AD7322
Preliminary Technical Data
When the ADC starts a conversion (Figure ꢁ), SW2 will open
and SW1 will move to position B, causing the comparator to
become unbalanced. The control logic and the charge
redistribution DAC is used to add and subtract fixed amounts
of charge from the sampling capacitor arrays to bring the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
Control Logic generates the ADC output code.
Table 6. LSB sizes for each Analog Input Range
Input Range
1ꢀ0
Full Scale Range/4096 LSB Size
2ꢀ0/4ꢀ96
1ꢀ0/4ꢀ96
ꢁ0/4ꢀ96
4.882 m0
2.441 m0
1.22 m0
ꢁ0
2.ꢁ0
ꢀ to 1ꢀ0
1ꢀ0/4ꢀ96
2.441 m0
CAPACITIVE
DAC
COMPARATOR
C
S
B
A
Vin0
CONTROL
LOGIC
SW1
SW2
The ideal transfer characteristic for the AD7322 when Twos
Complement coding is selected is shown in Figure 8, and the
ideal transfer characteristic for the AD7322 when Straight
Binary coding is selected is shown in Figure 9.
AGND
Figure 5. ADC Conversion Phase(Single Ended)
Figure 6 shows the differential configuration during the
Acquisition phase. For the Conversion Phase, SW3 will open,
SW1 and SW2 will move to position B, see Figure 7. The output
impedances of the source driving the 0in+ and 0in- pins must
be matched; otherwise the two inputs will have different settling
times, resulting in errors.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
CAPACITIVE
DAC
COMPARATOR
C
B
S
-FSR/2 + 1LSB
+FSR/2 - 1LSB
Vin+
Vin-
V
- 1LSB
REF
A
A
SW1
SW2
CONTROL
LOGIC
SW3
ANALOG INPUT
C
S
B
Figure 8. Twos Complement Transfer Characteristic (Bipolar Ranges)
V
REF
CAPACITIVE
DAC
111...111
111...110
Figure 6. ADC Differential Configuration during Acquisition Phase
CAPACITIVE
DAC
111...000
011...111
COMPARATOR
C
B
S
Vin+
Vin-
A
A
SW1
SW2
CONTROL
LOGIC
SW3
000...010
000...001
C
B
S
V
REF
CAPACITIVE
DAC
000...000
1LSB
FSR/2 -1LSB
ANALOG INPUT
-FSR/2
Figure 7. ADC Differential Configuration during Conversion Phase
Figure 9. Straight Binary Transfer Characteristic (Bipolar Ranges)
Output Coding
ANALOG INPUT
The AD7322 default output coding is set to two’s complement.
The output coding is controlled by the Coding bit in the
Control Register. To change the output coding to Straight
Binary Coding the Coding bit in the Control Register must be
set. When operating in Sequence mode the output coding for
each channel in the sequence will be the value written to the
coding bit during the last write to the Control Register.
The analog inputs of the AD7322 may be configured as Single-
Ended, True differential or Pseudo Differential via the Control
Register Mode Bits as shown in Table 9 of the Register Section.
The AD7322 can accept True bipolar input signals. On power
up the Analog inputs will operate as 2 Single-Ended Analog
Input Channels. If True Differential or Pseudo Differential is
required, a write to the Control register is necessary to change
this configuration after power up.
Transfer Functions
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is dependant
on the Analog input Range selected.
Figure 1ꢀ shows the equivalent Analog input circuit of the
AD7322 in Single-Ended Mode. Figure 11 shows the equivalent
Analog input structure in Differential mode. The Two Diodes
provide ESD protection for the Analog Inputs.
Rev. PrE | Page 10 of 18
ATMEL [ ATMEL ]
